1. Field of the Invention
This invention relates to a level conversion circuit which is adaptable to, for example, a logic circuit.
2. Description of the Related Art
FIG. 3 shows a conventional level conversion circuit. Input node 1 is connected to the drain of N-channel field effect translator 2 in the depletion type. The gate of this transistor 2 is connected to power source V.sub.DD, and the source thereof is connected to the gate of enhancement type P-channel field effect transistor 4 and that of enhancement type N-channel field effect transistor 5. The source of the transistor 4 is connected to the power source V.sub.DD, and the drain thereof is connected to output node 6. The drain of the transistor 5 is connected to the output node 6, and the source thereof is connected to the power source V.sub.SS.
As regards the conventional level conversion circuit as described above, in order to make inverter circuit 3 perform the static operation, threshold voltage V.sub.TH of the depletion type N-channel transistor 2 must be set at less than 0 V. Further, this threshold voltage V.sub.Th must be set at more than -0.3 V or -0.4 V, in order to prevent the high voltage from being supplied to the gates of the transistors 4 and 5, when the voltage higher than that of the power source V.sub.DD is input to the input node 1. Therefore, the design margin of the transistor 2 is small. For this reason, the threshold voltage V.sub.TH of the transistor 2 is easily variable with reference to variety of manufacturing processes and changes of the temperature, and stable operations thereof are hardly maintained.
The integrated circuit as shown in FIG. 3 includes the enhancement type transistors and the depletion type transistor. The manufacturing steps of the integrated circuit including the transistors in both types are more than those of an integrated circuit constituted by only enhancement type transistors and then, there will be a problem that the manufacturing cost increases.